The present invention relates generally to semiconductor processing. In particular applications the invention pertains to methods of forming capacitor structures and methods of resist removal.
Increased performance, both with regard to more complex functionality and higher speeds, is a continuing goal of efforts in advancing the semiconductor arts. One method that has been used for achieving this goal is scaling downward the size of individual devices used in forming advanced semiconductor integrated circuits. However, it is found that at times, changes in the components used in fabricating such down-sized devices are advantageous. For example, where capacitors, such as those used in memory integrated circuits, are scaled downward in size, dielectric materials such as silicon oxide and silicon nitride are often replaced with alternate materials having a higher dielectric constant to achieve desired capacitance. Where such replacements of dielectric materials are made, it can be advantageous to form capacitor electrodes comprising one or more of platinum, tantalum, ruthenium, iridium, and titanium. Such electrodes can comprise, for example, alloys of various metals and/or nitrides of various metals, including, for example, titanium nitride. The capacitors comprising metallic electrodes are well known in the art, and are frequently described as metal-insulator-metal capacitor constructions.
One method for patterning various dielectric and conductive materials is chemical mechanical polishing (CMP). A material (such as platinum), can be blanket formed within an opening and over surfaces proximate the opening. The material can be removed from over the surfaces by a CMP method. The material within the opening, elevationally below that upper surface, will not be removed. The material within the opening can ultimately form a capacitor electrode structure. A problem with the CMP method can be scratching or smearing of the material, which can prevent the proper forming of the ultimately desired capacitor structure. For instance, if the material is platinum or an alloy of platinum, scratching or smearing of the platinum can occur in a CMP process. It can be difficult, and for all practical purposes impossible, to remove smeared platinum from within a container.
It would be desirable, to develop a CMP method where the removal of portions of various materials (such as platinum or barrier materials) can be effected without scratching or smearing across surfaces of the materials. It would also be desirable if such a CMP method was cost-effective and could be performed using essentially standard CMP processing tools.
In one aspect, the present invention can provide methods for forming structures (such as capacitor or plug structures) and/or removing resist from a semiconductor substrate. A material is formed over a substrate, and a resist layer is formed over the material. Subsequently, at least a portion of the resist layer is removed to expose a desired portion of the material. The resist layer can be removed by providing contact of a chemical mechanical polishing pad and a polishing fluid with the resist layer. Such contact can be provided by a chemical mechanical polishing system that encompasses a mechanism for moving the polishing pad and/or the substrate. In some embodiments of the present invention it is advantageous to provide that the polishing fluid has a particle concentration of less than or equal to about 0.1% by weight of a silica-comprising material, and in particular embodiments it is advantageous for the polishing fluid to be essentially free of particles. In particular aspects, the polishing fluid can comprise tetramethylammonium hydroxide (TMAH) or ammonia to increase a rate of removal of various compositions by the fluid.
Some embodiments of the present invention provide for forming a recess within the semiconductor substrate prior to forming the material that is to be covered by the resist. For such embodiments, the material can be formed to partially fill the recess and extend outward over an upper surface of the semiconductor substrate. The resist layer can be formed within the partially filled recess.
A suitable semiconductor substrate can encompasses a semiconductive portion and an overlying insulative portion. For embodiments that encompass a recess, such recess can be formed within the insulative portion. In some embodiments the recess extends to expose, at a bottom and/or sidewalls of the recess, a portion of the semiconductive portion or a portion of a conductive device formed over or in the semiconductive portion. Where the material encompasses a conductive material, electrical communication between the conductive material and the semiconductive portion or conductive device can be provided through the bottom or sidewalls of the recess. In some embodiments of the present invention, the material can include more than one layer. For example, the material can encompass a first layer of a first composition and a second layer of a second composition overlying the first layer. The two compositions can be, for example, a first composition comprising metal and both of nitrogen and silicon (such as TaSiN); and a second composition consisting essentially of metal and nitrogen (such as TaN).